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? The team is responsible for the complete verification lifecycle, from system-level concept to tape out and post-silicon support.
? The responsibility of the position involves comprehensive pre-silicon test planning for digital power IP's, its testbench development using the advanced verification methodology such as System-Verilog-UVM, coverage development, assertion model development and formal verification (property checking)
? Learn and deploy power aware UPF verification flow and methodologies.
? Involve in developing automation to improve verification efficiency.
? Meeting with product designers to determine functionality protocols.
? Reviewing the product designs and noting likely points of failure.
? Designing verification methodology based on product designs and failure points.
? Determining testing environments and verification tools.
? Reviewing existing engineering criteria for similar products.
? Planning the method of sequence for testing operations.
? Instituting and tweaking testing mechanisms and protocols.
? Conducting quality control inspections.
? Writing up final test procedures and training QC staff.
? Bachelor’s Degree in Science, Engineering, or related field and 7+ years of ASIC design, verification, or related work experience
? Minimum 5 years of DV experience using UVM/assertion-based verification technologies.
? Experience in VHDL, Verilog and/or System-Verilog, Assertions, C/C++ and scripting.
? Experience in verifying complex SOC or SOC subsystems.
? Experience with using memory verification VIPs.
? Exposure to firmware/driver development using C/C++.
? Exposure to multiple successful tape-outs from conception to post silicon debug to production release.
? Detailed knowledge of testing methodology.
? Knowledge of design processes and quality control procedures.
? Knowledge of automated testing and electrical testing systems and tools.
? Excellent analytical and troubleshooting skills.
? A good eye and attention to detail.
? Advanced verbal and written communication skills.
? The team is responsible for the complete physical design lifecycle, from floor planning, place and route, timing/power analysis, physical verification DRC/LVS, chip finishing to tape out and post-silicon support.
? The responsibility of the position involves placement of memory blocks and analog hard macros, power grid design, analog routing plus shielding, addressing routing congestion and crosstalk noise avoidance.
? Designing robust power grid, performing power estimation, IR drop and EM analysis.
? Resolving DRC/LVS issues and performing chip finishing for tape out.
? Supporting functional ECO design changes, identifying logic changes using spare gates, with minimal metal changes.
? Actively work with the design team to resolve implementation and timing issues.
? Involve in developing script automation to improve implementation efficiency.
? Reviewing existing engineering criteria for similar products.
? Conducting quality control inspections.
? Bachelor’s Degree in Science, Engineering, or related field and 12+ years of ASIC implementation or related work experience
? Minimum 8 years of P&R experience, preferably using Cadence tools.
? Experience in VHDL, Verilog and/or System-Verilog and scripting languages.
? Experience in advance process nodes 16nm and below.
? Experience with logic libraries and PDKs, with different track libraries and multi-voltage standard cells (GO1/GO2).
? Experience with timing analysis, power estimation and IR drop analysis.
? Experience with debugging and resolving DRC/LVS issues.
? Knowledge of IO padring, packaging, flip-chip/wire-bonding, IBIS models.
? Exposure to multiple successful tape-outs from conception to post silicon debug to production release.
? Knowledge of design processes and quality control procedures.
? Knowledge of wafer manufacturing procedures.
? Excellent analytical and troubleshooting skills.
? A good eye and attention to detail.
? Advanced verbal and written communication skills.
? The team is responsible for the complete implementation lifecycle, from logic synthesis of design into technology specific mapping to tape out and post-silicon support.
? The responsibility of the position involves developing synthesis constraints to meet performance, power and area targets and logic equivalence check of RTL with mapped design.
? Linting of RTL code to ensure quality of design.
? Detailed analysis of asynchronous clock domain crossings to ensure proper synchronization.
? Verification of power domain crossings for correct implementation of level shifters and isolation.
? Supporting functional ECO design changes, identifying logic changes including formal equivalency check.
? Actively work with the design team to resolve implementation and timing issues.
? Involve in developing script automation to improve implementation efficiency.
? Reviewing existing engineering criteria for similar products.
? Conducting quality control inspections.
? Bachelor’s Degree in Science, Engineering, or related field and 12+ years of ASIC implementation or related work experience
? Minimum 8 years of synthesis experience, preferably using Cadence tools.
? Experience in VHDL, Verilog and/or System-Verilog and scripting languages.
? Experience in advance process nodes 16nm and below.
? Experience with logic libraries and PDKs, with different track libraries and multi-voltage standard cells (GO1/GO2).
? Experience with static timing analysis, CDC and RDC checks.
? Experience with UPF multi-power domain designs and verification of power domain crossings.
? Exposure to multiple successful tape-outs from conception to post silicon debug to production release.
? Knowledge of design processes and quality control procedures.
? Knowledge of wafer manufacturing procedures.
? Excellent analytical and troubleshooting skills.
? A good eye and attention to detail.
? Advanced verbal and written communication skills.
? The team is responsible for the complete Design for Test (DFT) implementation. from design to logic synthesis of DFT design into technology specific mapping to tape out and post-silicon support.
? The responsibility of the position involves working with Marketing, Probe, Assembly, Test, Process Integration, CAD, Verification Engineering and Product Engineering groups to ensure proper testing and manufacturability of product.
? Work closely with Product Engineering to ensure that test mode definitions, and documentation include all required functionality.
? Design, standardize, and document test methods and modes to facilitate common test flows and coverage on all designs.
? SoC DFT architecture specification including test muxing and DFT RTL coding.
? Understand the current manufacturing test flow to provide circuit advice to entire department.
? Ensure that new technologies include the needed test mode designs to allow for full fail coverage testing.
? Improving, extending and porting existing DFT circuits and concepts to all FPGA family members.
? Execute Automatic Test Pattern Generation (ATPG), including insertion, conduct the pattern re-simulation and gate level simulation.
? Memory BIST insertion, validation and pattern generation, IEEE1149.1 Boundary Scan design.
? Supporting failure analysis and helping with silicon bring-up and debug.
? Will assist with silicon debug in the event of yield limiting issues or returned materials.
? Assist Verification Engineering with test mode verification plans.
? Use scripting languages to automate process flow.
? Bachelor’s Degree in Science, Engineering, or related field and 12+ years of ASIC implementation or related work experience
? Minimum 8 years of design experience, preferably using Cadence tools.
? The candidate should be familiar with ASIC/Logic design flow including verilog coding, verification, RTL/full chip simulation, timing closure, and ECO.
? Experience with advanced technology nodes required (90nm, 40nm, 28nm, 20nm, 16nm)
? Understanding of Design for Test methodologies and DFT verification experience is preferred.
? Basic working knowledge on V93 tester is a big plus.
? Strong background on Scan/ATPG/Compression/Memory Test.
? Strong fundamental knowledge of DFT techniques - Understanding of core-based test methodology and scan isolation.
? Tessent Shell/Testkompress for ATPG, Tessent MBIST, Cadence NCSIM, Synopsys DFTMAX and TetraMAX.
? Exposure to multiple successful tape-outs from conception to post silicon debug to production release.
? Excellent analytical and troubleshooting skills.
? The team is responsible for the complete implementation lifecycle, from design to logic synthesis of design into technology specific mapping to tape out and post-silicon support.
? The responsibility of the position involves developing design specifications for different functional blocks on a chip, Create microarchitecture diagrams of functional blocks, Design functional blocks using Veriog / System Verilog RTL code, conduct Synthesis and place and route to meet timing / area goals.
? Run Synthesis, Equivalence Checking, Clock-Domain Crossing (CDC) Analysis, Area/Power optimizations, Linting, Static Timing Analysis (STA).
? Detailed analysis of asynchronous clock domain crossings to ensure proper synchronization.
? Design of power domain crossings for correct implementation of level shifters and isolation.
? Supporting functional ECO design changes, identifying logic changes including formal equivalency check.
? Interacting closely with other teams such as the Architecture, Applications, Product and Test Engineering, and Validation.
? Support Validation of the IP/SoC on FPGA platform and support FPGA code development.
? Developing design, verification and validation tools and flows, as needed.
? Conducting and subjecting to documentation and code reviews.
? Contributing to test plans and calling out design and verification requirements for tracking.
? Involved in developing script automation to improve implementation efficiency.
? Bachelor’s Degree in Science, Engineering, or related field and 12+ years of ASIC implementation or related work experience
? Minimum 8 years of design experience, preferably using Cadence tools.
? Experience in VHDL, Verilog and/or System-Verilog and scripting languages.
? For Logic design, experience with Logic Synthesis, Linting, CDC/RDC and DFT tools is preferred.
? Experience with advanced technology nodes required (90nm, 40nm, 28nm, 20nm, 16nm)
? Experience with Microarchitecture, RTL, Synthesis and STA.
? Experience with high performance techniques and power measurement & analysis.
? Experience with UPF multi-power domain designs and verification of power domain crossings.
? Exposure to multiple successful tape-outs from conception to post silicon debug to production release.
? Knowledge of design processes and quality control procedures.
? Experience in interfacing with architecture and Physical implementation teams is a plus.
? Strong scripting skills, with Perl, Python, etc.
? Excellent analytical and troubleshooting skills.
? The team is responsible for design activities including research, definition, and designing of analog blocks and sub-systems of application specific integrated circuits.
? Design, simulation, layout verification, characterization, and release to production of integrated circuits.
? Supporting product definition teams to develop product requirements and specifications.
? Analyzing and developing chip architectures to meet required compliance and performance.
? Creating transistor level analog circuit designs and verifying those designs using circuit-level and behavioral level simulators.
? Develop analog IP blocks such as PLL, IRC, FRO, ADC, LDO, DC-DC, DAC, CMP that will be embedded in Microcontroller designs.
? Expected to be involved in all aspects of the analog design process from schematic design to validation of circuits in the lab.
? Running all necessary physical design verification (LVS/DRC/ERC, etc) to clean blocks in the SoC Design flow
? Drive and contribute to silicon bench characterization, support ATE production test development.
? Effectively communicate results by preparing written reports and making presentations describing analyses performed, solutions developed, and value obtained.
? Bachelor’s Degree in Science, Engineering, or related field and 12+ years of ASIC Analog implementation or related work experience
? Minimum 8 years of Analog design experience, preferably using Cadence tools.
? Understanding of circuit analysis, experience with layout, and understanding of signals and systems a must.
? Experience designing tight matching, low noise, and low power analog blocks, resistors, capacitors, pad IO's, ESD structures.
? Strong background with standard analog simulators such as PSPICE, HSPICE, Spectre, and AMS simulation.
? High level proficiency in interpretation of CALIBRE DRC, ERC, LVS, etc.
? Ability to improve design development and testing efficiency through scripting using Perl/Python.
? Strong communication and inter-personal skills, developing/driving concepts and ideas with other team members and across other parts of a large organization (or other companies.
? Characterize and validate mixed-signal IP circuits for various leading edge Si technologies.
? Develop characterization plans for IPs to be characterized.
? Execute characterization, collect & analyze data, and prepare final report.
? Work closely with design teams on DFT (Design For Test) and characterization techniques.
? Continually innovate more efficient test techniques to save on cost and time.
1. Customer Needs Analysis and Delivery Implementation: Engage with smart hardware product companies to conduct market research, identify emerging trends, and collaboratively innovate new demands. Through joint user research and competitive product analysis with end-product companies, clarify the target users, usage scenarios, and core functionalities of the product, ensuring accurate product positioning and functional requirements. Deeply participate in customer product planning, foster stronger collaboration, and expedite the implementation of product solutions. Coverage areas include but are not limited to smart toys, smart home devices, medical and health care, robotics, wearable devices, and various IoT products.
2. Product & Solution Planning: Collect and analyze feedback from B2B clients and end-users, refine product requirements, and drive the resolution of product issues. Leverage the company's existing technological strengths to develop development plans and roadmaps for hardware and software solutions, defining phased goals and directions for product and technical solutions.
3. Collaborative Technology Planning: Monitor advancements in artificial intelligence technologies and product development directions. Adjust product strategies in line with industry, market, and user trends to enhance product competitiveness, and collaborate with the technical team to create a technology development roadmap.
4. Business Model Design: Design business models and oversee business planning, including future product development and industry chain collaborations.
5. Pricing and Marketing Collaboration: Participate in pricing strategy formulation, determining reasonable prices based on cost, market demand, and competitive landscape. Collaborate with the marketing team to develop promotion and marketing strategies to increase market share and sales.
6. Partner Relationship Management: Establish and maintain strong relationships with upstream and downstream partners such as smart hardware manufacturers, cloud service providers, and software developers to secure technical support and resources, and drive the ecosystem development of the product.
1. Experience: A minimum of 5 years of experience as a product manager, with preference given to those with experience in AI hardware products, consumer electronics, or AI robotics industries.
2. Market Analysis: Stay attuned to the dynamics and trends of the AI hardware market, understanding the industry's direction and competitive landscape. Capable of analyzing and interpreting market data to inform product positioning and marketing strategies.
3. Understanding of AI Technology: Possess a deep understanding of fundamental AI concepts and algorithmic principles (such as machine learning, deep learning, etc.), and be able to comprehend the application scenarios and advantages of various AI technologies in hardware products. For example, knowing how to utilize image recognition algorithms to implement facial recognition features in smart camera products.
4. Hardware Fundamentals: Have a solid grasp of basic hardware knowledge, including circuit principles, chip technology, sensor technology, and embedded systems. Maintain a certain level of awareness regarding the technological developments in consumer electronics and smart hardware.
5. Innovation Capability: Ability to continuously propose new product concepts and design ideas, providing differentiated competitive advantages for the product.
6. Team Collaboration: Effectively communicate and collaborate with cross-functional team members, including hardware engineers, software engineers, algorithm engineers, designers, and marketing personnel. Understand the needs and working styles of different teams to foster cooperation and jointly drive product development and promotion.
7. Education: Hold a full-time bachelor's degree or higher in computer science, electronic information, automation, mechanical engineering, or related fields.
1. Market Analysis: Skilled in gathering and analyzing market information, understanding the market demand for AI hardware, customer needs, and competitor landscape. Capable of formulating corresponding business strategies and marketing plans based on market analysis results.
2. Client Development: Possesses strong client development capabilities, actively seeking out potential clients and establishing as well as maintaining good client relationships. Understands clients' business needs and application scenarios, providing suitable AI hardware solutions to drive client project progress and achieve sales targets.
3. Business Negotiation: Exhibits excellent business negotiation skills, effectively communicating and negotiating with clients and partners on pricing, cooperation models, contract terms, etc., to secure favorable cooperation conditions.
4. Marketing Promotion: Develops and implements marketing promotion plans, such as website updates, creating promotional product brochures, short videos, company promotional videos, online promotion, participating in industry exhibitions, joining industry associations, and conducting training and empowerment sessions.
5. Resource Integration: Adept at integrating internal and external resources, including supplier resources, partner resources, and client resources, to establish a broad business cooperation network. Capable of fully utilizing various resources to support the company's business development.
6. Project Management: Possesses certain project management abilities, capable of coordinating internal departments such as R&D, production, sales, and after-sales service to ensure the smooth progress of business projects. Able to develop project plans, monitor project progress, resolve issues that arise during projects, and ensure timely delivery and satisfaction of client needs.
7. Technical Understanding: Has a certain understanding of AI hardware technology principles, architecture, performance metrics, etc., to facilitate effective communication with technical teams and clients.
8. Business Review and Reporting: Regularly reviews the responsible clients or business segments, collects industry intelligence, and forms industry trend reports.
1. A bachelor's degree or higher is required, with preference given to majors in electronic engineering, integrated circuits, computer science, communication engineering, and other related STEM fields.
2. Candidates should have a certain number of years (typically 3 or more) of work experience in industries such as AI hardware, semiconductors, consumer electronics, AI robotics, or related high-tech sectors. Experience working in AI hardware companies is a plus.
3. English Proficiency: Given the high level of internationalization in the AI hardware industry, strong English listening, speaking, reading, and writing skills are essential for smooth communication with international clients and partners.
4. Stress Resistance: The ability to withstand pressure is crucial, maintaining good performance in high-stress environments and actively addressing various difficulties and challenges.
5. Communication Skills: Excellent communication skills, both verbal and written, are necessary. The candidate should be able to effectively communicate with individuals at different levels, such as reporting to senior management, discussing technical issues with the tech team, and communicating business needs with clients. They should be able to clearly convey business information and accurately understand the intentions and needs of others.
6. Team Collaboration: Strong team spirit is required, with the ability to work closely with various departments within the company to complete business projects together. The candidate should actively participate in team discussions and decision-making, sharing their experiences and insights to contribute to the team's development.
1. Responsible for designing the MCU-based motor control software framework and decomposing software requirements according to project needs.
2. Responsible for developing mainstream control algorithms for various types of motors (such as PMSM, BLDC, induction motors, etc.) based on requirements.
3. Responsible for building Simulink models for control algorithms or implementing them in embedded C code.
4. Responsible for defining the requirements of underlying driver software based on the software framework.
5. Responsible for integrating control algorithm software, conducting joint software-hardware debugging, and debugging the motor system.
6. Complete tasks assigned by superiors.
1. Bachelor's degree or higher in Electronic Engineering, Automation, Electrical Engineering, Computer Science, or related fields; a Master's degree is preferred.
2. Over 3 years of work experience with a solid theoretical foundation and practical experience in motor control.
3. Proficient in C/assembly language, with preference given to those with experience in MATLAB/Simulink algorithm simulation and analysis.
4. Experience in motor control engineering development using microcontrollers from TI, Renesas, ST, NXP, Infineon, etc.
5. Expertise in SPWM, SVPWM, six-step control, FOC, field-weakening control, and related applications; proficiency in sensorless control algorithms is preferred.
6. Strong communication skills, a sense of responsibility, and self-motivation.
1. Product Sales: Responsible for the sales of integrated processor products, including promotion, negotiation, and contract signing, ensuring the achievement of sales targets.
2. Market Development: Explore new markets and clients to expand the product's sales reach.
3. Customer Relationship Maintenance: Maintain existing customer relationships, establish long-term strategic partnerships, and conduct regular follow-ups with clients.
4. Technical Support: Coordinate with the technical team to provide professional technical support services to customers, resolving issues related to product usage.
5. Market Information Collection: Gather market information and conduct competitor analysis to provide insights for the company's market strategies.
6. Internal Coordination: Maintain effective communication with internal departments to ensure smooth order execution and delivery.
7. After-Sales Service: Assist in handling customer after-sales matters to enhance customer satisfaction.
8. Sales Strategy Development: Develop and execute sales strategies, participate in market activities, and improve the product's market share.
1. Educational Background: Bachelor's degree or higher, with preference given to majors in electronics, automation, or related fields.
2. Work Experience: 1-3 years of relevant sales experience, with preference given to those with sales experience in the microcontroller industry.
3. Technical Knowledge: Familiar with processor product knowledge and its application areas, especially in industrial control, medical, and automotive fields.
4. Communication Skills: Possess excellent communication and interpersonal skills, capable of independently conducting client visits and business negotiations.
5. Stress Resistance: Able to handle work pressure, with a strong sense of responsibility and team spirit.
6. Learning Ability: Strong learning ability and motivation, capable of quickly mastering new product knowledge and market trends.
1. Responsible for the customized development and verification of Eclipse-based Integrated Development Environment (IDE), and completing relevant technical documentation.
2. Responsible for the development and verification of Eclipse-based plugins, including the design, development, and integration of graphical interfaces.
3. Responsible for integrating Eclipse-based embedded debugger drivers, such as Jlink and OpenOCD.
4. Identify common customer requirements, independently decompose requirements, and complete detailed design and coding implementation.
5. Prepare software-related requirements, design, and testing documentation.
6. Complete other tasks assigned by the team leader.
1. Bachelor's degree or higher in Computer Engineering or other related fields.
2. Familiar with the architecture, principles, and underlying implementation of Eclipse IDE.
3. Proficient in Java programming and experienced in graphical interface development.
4. Possess experience in plugin and RCP development within the Eclipse IDE framework.
5. Familiar with embedded debugging operations and principles in the Eclipse IDE framework, such as JLink and OpenOCD.
6. Strong ability to analyze software requirements, formulate development plans, and execute development tasks.
7. Creative, willing to delve into technology, with excellent communication and teamwork skills.
8. Preference will be given to candidates with experience in IDE development for related MCU products.
1. Collect, organize, and analyze hardware requirements, formulate hardware development plans, and conduct hardware framework design, chip selection, etc.
2. Complete the schematic design and PCB Layout for each functional unit circuit based on hardware requirements.
3. Develop product specifications, test specifications, and technical documents according to design requirements.
4. Formulate test plans for each functional circuit, and complete the debugging and testing of hardware products.
5. Be responsible for the selection, evaluation, verification, and supplier management of hardware components.
6. Process improvement and quality control; propose suggestions for process improvement and conduct quality control for hardware products.
1. Bachelor's degree or higher in Power Electronics, Electronic Information, Electrical Engineering and Automation, Automation, Automotive Electronics, or related fields.
2. Possess three or more years of hardware development experience, with experience in automotive-grade MCU development and benchmarking against competitors such as IFX TC2XX, TC3XX, NXP FS32K series products, etc.
3. Familiar with MCU system architecture and peripheral interfaces, such as I2C, SPI, UART, ADC, USB, POWER, and knowledgeable about CAN and LIN bus protocols.
4. Proficient in using relevant hardware development and debugging tools.
5. Familiar with hardware development and quality management processes.
6. Preference will be given to candidates with audio hardware development experience and familiarity with electroacoustic device (Speaker, MIC, Receiver, etc.) interface chips and communication protocols.
7. Possess a research-oriented mindset, strong sense of responsibility, excellent communication skills, and team spirit.
1. Establish and improve the company's administrative management regulations and systems, such as office supplies management systems, and supervise their implementation to ensure effective enforcement of all regulations.
2. Responsible for organizing and arranging company meetings, including large-scale annual meetings, management meetings, as well as planning and implementing employee activities.
3. Oversee the maintenance and optimization of the office environment, establish procurement and management mechanisms for fixed assets, facilities, and office supplies, and control company administrative expenses.
4. Responsible for organizing, archiving, and managing important company documents and contracts to ensure accuracy and confidentiality of information.
5. Possess excellent planning, organizational, and execution skills, capable of formulating and implementing administrative strategies and plans, optimizing administrative processes, and improving work efficiency.
6. Coordinate daily operations of various projects and manage the work arrangements of branch office operational staff.
7. Organize company decision-making meetings and promote the implementation of meeting-related matters.
8. Develop and implement project plans, monitor project execution, and control project quality.
9. Prepare project operation plans and budgets, control annual budget costs, and analyze project revenue and costs.
10. Assist in executing project operations, arrange reasonable schedules, and handle emergencies.
11. Recruit, select, and train potential candidates, and provide recommendations for human resource replenishment to the company.
12. Complete other tasks assigned by the General Manager.
1. Bachelor's degree or higher, with 3-5 years of practical work experience in administrative management or related fields.
2. Capable of managing and controlling administrative budgets, allocating resources reasonably, and achieving cost-effectiveness.
3. Preference will be given to candidates with experience in high-tech or policy application projects.
4. Possess relevant work experience in group or regional positions.
5. Demonstrate strong professional ethics, a high sense of work responsibility, and career dedication.
1. Daily Administrative Affairs Management: Responsible for handling company courier services, invoice reimbursements, property management communications, and plant maintenance to ensure a clean and orderly operational environment.
2. Meeting and Event Coordination: Manage conference room bookings and arrangements, assist in planning and organizing internal training and team-building activities, ensuring smooth execution of events.
3. Office Supplies Management: Oversee the procurement, inventory management, and record-keeping of office supplies to ensure timely replenishment and proper allocation.
4. Effective Recruitment Assistance: Assist in completing recruitment tasks and achieving monthly recruitment plans.
5. Personnel Management: Support the HR department in recruitment, training, employee onboarding/offboarding, and related tasks.
6. Attendance Management: Track employee attendance, leave, and overtime to ensure the smooth operation of company administrative work.
Operations Management:
1. Policy Collection: Collect and study the latest government policies and incentives, including honorary titles, tax benefits, R&D subsidies, and innovation funds. Provide in-depth policy analysis and recommendations to decision-makers and monitor policy implementation outcomes.
2. Project Management: Summarize, edit, and maintain all internal and external project materials, including project proposals and PPTs, ensuring completeness and accuracy.
3. Project Application: Liaise with government departments to facilitate policy applications, ensuring the company fully utilizes national and local preferential policies and secures optimal policy support.
1. Bachelor's degree or higher.
2. Possess excellent communication, expression, organizational coordination, and interpersonal skills.
3. Proficient in using office software such as WORD, EXCEL, and PPT.
4. Strong communication, negotiation, and coordination skills, with a high sense of responsibility and initiative.
5. Honest and trustworthy, with a strong sense of work responsibility and team spirit.
6. Capable of working independently to ensure work quality and efficiency.
7. Preference will be given to candidates with good English proficiency.
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Tel +86?573?82828169
Address Unit 1-1, Building 14, Xindeyuan, Fund Town, No. 1856 Nanjiang Road, Dongzha Street, Nanhu District, Jiaxing City, Zhejiang Province, PRC
Tel +86?21?60711407
Address Room 203, Building 7, Zhangjiang Micro Electron Port, No. 690 Bibo Road, Pudong New District, Shanghai, PRC
Address 227 W. Alcala Avenue, Mountain House, CA 95391-1401 USA
Emailinfo@istarchip.com
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